Index of /intel-research/silicon

(1)

Intel

1

Intel's 90 nm Process Starting

High Volume Manufacturing

Mark Bohr

Intel Senior Fellow

Director of Process Architecture & Integration

(2)

Intel

2

A New Process Every 2 Years

Process Name P854 P856 P858 Px60 P1262 P1264

1st _Production ₁₉₉₅ ₁₉₉₇ ₁₉₉₉ ₂₀₀₁ ₂₀₀₃ ₂₀₀₅

Lithography 0.35µm 0.25µm 0.18µm 0.13µm 90nm 65nm

Gate Length 0.35µm 0.20µm 0.13µm <70nm <50nm <35nm

Wafer (mm) 200 200 200 200/300 300 300

(3)

Intel

3

90 nm Generation Transistor

Nickel Silicide Layer

Silicon Gate Electrode

1.2 nm SiO₂ Gate Oxide

Strained Silicon

50nm

(4)

Intel

4

Typical Feature Size Scaling

0.01 0.1 1 10

1970 1980 1990 2000 2010 2020

Micron

0.01 0.1 1 10 3.0um .18um .25um .35um .5um .8um 1.0um 1.5um 2.0um .13um 90nm

Feature size scaling has accelerated 0.7x / 3 year

(5)

Intel

5

Transistor Gate Length Scaling

0.01 0.1 1 10

1970 1980 1990 2000 2010 2020

Micron

0.01 0.1 1 10 3.0um .18um .25um .35um .5um .8um 1.0um 1.5um 2.0um .13um 90nm 50nm Gate Length

Faster gate length scaling to maintain transistor performance lead 0.7x / 3 year

(6)

Intel

6

Gate Oxide Scaling

1 10

1990 1995 2000 2005

Gate Oxide Thickness

(nm)

1 10

Intel leads the industry in gate oxide scaling

Thinner gate oxide increases transistor performance

90nm .13um

.18um .25um

.35um

Generation

(7)

Intel

7

90 nm Generation Gate Oxide

Polysilicon Gate Electrode

Silicon Substrate

1.2 nm SiO₂

(8)

Intel

8

Strained Silicon Transistors

Current Flow

Normal electron flow

Faster electron flow

Normal Silicon Lattice Strained Silicon Lattice

(9)

Intel

9

NiSi for Low Gate Resistance

0 5 10 15

0 100 200

Gate size (nm)

Resistance (

Ω

/ sq) CoSi2

NiSi

(10)

Intel

10

Transistor Performance

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

1990 1995 2000 2005

Drive Current (mA/um) 1 10 Supply Voltage (V) NMOS PMOS

Highest drive current in the industry Reduced supply voltage for lower power

(11)

Intel

11

90 nm Generation Interconnects

M7

M6

M5

M4

M3

M2

M1 Low-k CDO

Dielectric

Copper Interconnects

(12)

Intel

12

Low-k Carbon Doped Oxide

• New low-k CDO material used for interconnect dielectric

• Low-k CDO provides ~20% capacitance reduction over previous generation

• Lower interconnect capacitance results in faster interconnects

• Process integration and package assembly issues with this new material have been solved

Cu

CDO SiN

SiN

Cu

(13)

Intel

13

2-Layer Interconnect Dielectric Stack

• Intel uses a simple 2-layer dielectric stack:

Low-k CDO dielectric SiN etch stop

• Many of our competitors use a more complex 4-layer stack:

Dielectric Etch stop Dielectric Etch stop

• Intel's simpler stack is less costly and reduces capacitance by not having extra etch stop layer

(14)

Intel

14

Package Technology

Package

Integrated Heat Spreader Chip

(15)

Intel

15

1.0

µ

m

2

SRAM Cell

• Ultra-small SRAM cell packs six transistors in an area of 1.0 µm2

• Intel was first in the industry to reach this cell size milestone

• Small memory cell enables cost

effective increase in CPU performance by adding more on-die cache memory

(16)

Intel

16

52 Mbit SRAM Chip

109 mm2 _{die size}

330 million transistors First silicon: Q1 2002

(17)

Intel

17

90 nm CPU Chips

Prescott CPU Dothan CPU

112 mm2 _{die size}

125 million transistors

87 mm2 _{die size}

144 million transistors

(18)

Intel

18

Yield Trend

1997 1998 1999 2000 2001 2002 2003 2004

Defect Density (log scale)

0.18µm 0.13µm 0.13µm 90nm

200mm 200mm 300mm 300mm

(19)

Intel

19

Summary

• Intel's 90 nm process incorporates industry-leading

transistor features and will be the first to use strained

silicon technology in volume manufacturing

• High density, high performance interconnects are

provided with 7 layers of copper combined with a new

low-k CDO dielectric and organic flip-chip packages

• Advanced CPU products are being ramped on this

technology

(20)

Intel

20

For further information on Intel's silicon technology,

please visit the Silicon Showcase at