Index of /intel-research/silicon

(1)

Cont inuing M oore 's La w

Cost Re duc t ion in N on

V ola t ile Se m ic onduc t or

M e m orie s

Cont inuing M oore 's La w

Cost Re duc t ion in N on

V ola t ile Se m ic onduc t or

M e m orie s

Stefan Lai, PhD Stefan Lai, PhD

Vice President, Technology and Manufacturing Group Vice President, Technology and Manufacturing Group

(2)

2

N

O

E

X

P

O

N

E

N

T

IA

L

I

S

F

O

R

E

V

E

R

.

N

O

E

X

P

O

N

E

N

T

IA

L

I

S

F

O

R

E

V

E

R

.

Gordon E. Moore

(3)

N O EX PON EN T I AL I S

FOREV ER . . .

N O EX PON EN T I AL I S

FOREV ER . . .

BUT

WE CAN DELAY

“

FOREVER

”

Gordon E. Moore

(4)

(5)

FLASH SCALI N G I S

RU N N I N G I N T O LI M I T S

FLASH SCALI N G I S

RU N N I N G I N T O LI M I T S

BUT

WE CAN DELAY

(6)

6

I nt e l ET OX ® (N OR) T e c hnology

Sc a ling

1993 / 0.6µm 1996 / 0.4µm 1986 / 1.5µm 1988 / 1.0µm 1991 / 0.8µm

1998 / 0.25µm 2000 / 0.18µm 2002 / 0.13µm 2004 / 90nm

5X _5X

Volume Production Year / Technology Generation

y

y 18+18+ years &years & 99 Generations of ETOXGenerations of ETOX®® (Intel NOR); High Volume (Intel NOR); High Volume Production starting for 90 nm

Production starting for 90 nm

y

y 7+7+ years andyears and 55 Generations of Intel StrataFlashGenerations of Intel StrataFlashTM TM _{(Multi Level}_{(Multi Level}

Cells 2bit / cell ) memory

(7)

I nt e l ET OX ® (N OR) T e c hnology

Sc a ling

1986 / 1.5µm 1988 / 1.0µm 1991 / 0.8µm 1993 / 0.6µm 1996 / 0.4µm

2000 / 0.18µm

1998 / 0.25µm _{2002 / 0.13}µ_m 2004 / 90nm

1/476

5X _5X

Volume Production Year / Technology Generation

y

y 18+18+ years &years & 99 Generations of ETOXGenerations of ETOX®® (Intel NOR); High Volume (Intel NOR); High Volume Production starting for 90 nm

Production starting for 90 nm

y

y 7+7+ years andyears and 55 Generations of Intel StrataFlashGenerations of Intel StrataFlashTM TM _{(Multi Level}_{(Multi Level}

Cells 2bit / cell ) memory

(8)

8

N V M e m ory T ra nsist ors

y

y Non volatile memory typically has a 10 year retention spec, Non volatile memory typically has a 10 year retention spec, requiring high energy barrier for electrons in floating gate

requiring high energy barrier for electrons in floating gate

y

y To overcome the high energy barrier, NV memory transistor To overcome the high energy barrier, NV memory transistor operates at much higher voltage compared to logic

operates at much higher voltage compared to logic

transistors

¾

¾ ~10V gate/ ~5V drain for ETOX_{~10V gate/ ~5V drain for ETOX}®_®

¾

¾ ~20V gate for NAND~20V gate for NAND

y

y NV transistors run into physical scaling limit earlier NV transistors run into physical scaling limit earlier compared to logic transistors

(9)

N OR Ga t e Le ngt h Sc a ling Lim it

Source Drain

+V_g

L_G

3.2 ev

e

-Programming

Hot e

-over barrier

Floating Gate Silicon Silicon

> 3.2 V

For Efficient Programming

~130nm

45nm

0 400 800 1200

.80µ 0.60µ 0.40µ0.25µ 0.18µ 0.13µ90nm 65nm 45nm 32nm

Litho Node LG

(10)

10

Floa t ing Ga t e Cha rge St ora ge Sc a ling

Estimated # Electrons Stored vs Litho Node

100 1000 10000 100000 1000000

0.01 0.1

1

Litho Node (Microns)

# El

ec

tr

ons

NAND # Electrons NOR # Electrons

y Cell capacitance (charge stored) decreases with cell

scaling while leakage mechanism remains the same -> larger Vt shift per electron

y Smaller NAND cell Æ Fewer Electrons

y MLC Charge Retention 1-2 generations more aggressive

(11)

I T RS Fla sh sc a ling proje c t ion

NOR NAND NOR NAND NOR NAND NOR NAND

Coupling ratio 0.65-0.75 0.65-0.75 0.6-0.7 0.6-0.7 0.6-0.7 0.6-0.7 0.6-0.7 0.6-0.7

Tunnel oxide (nm) 9-10 7-8 8-9 6-7 8-9 6-7 8 6-7

Interpoly oxide (nm) 12-14 13-15 8.5-10.5 10-13 8-10 10-13 4-6 9-10

Endurance (# cycles) 1E5 1E5 1E5 1E5 1E6 1E6 1E7 1E7

Retention (years) 10-20 10-20 10-20 10-20 10-20 10-20 20 20

NOR Iread (µA) 35-43 29-37 27-33 22-28

max. # bits per cell 2 2 4 4 8 8 8 8

2002 2007 2010 2016

Taken from the 2002 ITRS update

(12)

12

Sc a ling Opport unit ie s

Tunnel oxide

ONO

Poly 2

Contact

Electrical

Electrical

Resolution

Resolution Resolution_Resolution

Electrical &

Reliability

Electrical

Alignment

(13)

Opport unit ie s for 4 5 nm a nd be yond

y

Lithography: cornerstone for new technology node

y

Tight pitch/high aspect ratio processing

y

Tunnel oxide barrier engineering

y

ONO dielectric engineering

y

Floating gate material engineering

y

Channel engineering

y

(14)

(15)

(16)

N e w N V M e m ory

T e c hnologie s

(17)

N e w N V M e m ory T e c hnologie s

y

With the perceived difficulties of floating gate flash

memory scaling, many new memory technologies

were reported as possible replacement candidates

y

Most involve the introduction of new material and/or

new physical switching phenomena

How to choose between the

technologies?

(18)

18

Applied El

ectric Field

(19)

19

Applied El

ectric Field

(20)

20

Winning At t ribut e s

y

Memory market is well established, new entrants

must provide incentive for customers to use

something new

y

Cost is the most important incentive: but given the

learning curve, new entrants must have significant

node to node advantage to catch up

y

Functionality (performance, power etc) is difficult to

quantify: but customers tend to favor cost over

functionality (DRAM difficult to use, biggest memory

market segment)

Cost is the most important factor

(21)

Cost c onside ra t ion:

a Sim plifie d V ie w

Cost c onside ra t ion:

a Sim plifie d V ie w

y

y Any usable memory has to have mechanisms to read and Any usable memory has to have mechanisms to read and write. Two general ways to R/W:

write. Two general ways to R/W:

¾

¾ X_X-_-Y address in traditional memory architecture, with serial read _{Y address in traditional memory architecture, with serial read}

(CCD or NAND) as one variation (CCD or NAND) as one variation

¾

¾ Seek and scan similar to HDD_{Seek and scan similar to HDD}

y

y XX--Y addressable memory is limited by lithography and Y addressable memory is limited by lithography and follows Moore

follows Moore’’s Laws Law

y

y Seek and scan memory, no lithography, limited by scan Seek and scan memory, no lithography, limited by scan mechanism, size and density of storage areas in storage

mechanism, size and density of storage areas in storage

medium

(22)

22

X -Y Addre sse d Fla sh

y

y Transistors at cross point Transistors at cross point with wordlines and bitlines

with wordlines and bitlines

for cell selection and

read/write

y

y NAND memory is smaller NAND memory is smaller compared to NOR: no

compared to NOR: no

contact but also slower to

read

y

y Don_Don’’t see any new t see any new technology with X

technology with X--Y Y

address to be smaller than

NOR/NAND with MLC

(23)

Bre a k ing t he sc a ling ba rrie r

y

y Memory technologies requiring transistor switch will be first Memory technologies requiring transistor switch will be first limited in scaling

limited in scaling --> ETOX, NAND, FeRAM, MRAM; > ETOX, NAND, FeRAM, MRAM; diode diode switch scales better

switch scales better --> OUM, RRAM> OUM, RRAM

Ä

Ä Follows MooreFollows Moore’’s Law limited by transistor/diodes Law limited by transistor/diode

y

y Simple cross point switch with no transistor or diode more Simple cross point switch with no transistor or diode more scalable: molecular memories

scalable: molecular memories

Ä

Ä Continue MooreContinue Moore’s Law beyond transistor age’s Law beyond transistor age

y

y MultiMulti--layer memories have the potential to be lowest cost for layer memories have the potential to be lowest cost for litho defined memory

litho defined memory

Ä

Ä Drop below historical MooreDrop below historical Moore’’s Laws Law

y

y Seek and scan can be the lowest cost but involves new Seek and scan can be the lowest cost but involves new memory storage and sense mechanism

memory storage and sense mechanism

Ä

(24)

(25)

Bre a k ing t he sc a ling ba rrie r

y

y Memory technologies requiring transistor switch will be Memory technologies requiring transistor switch will be limited in scaling

limited in scaling -> FeRAM, MRAM, diode switch scales -> FeRAM, MRAM, diode switch scales better

better --> OUM, RRAM> OUM, RRAM

Ä

Ä Follows MooreFollows Moore’s Law limited by transistor/diode’s Law limited by transistor/diode

y

y Simple cross point switch with no transistor or diode more Simple cross point switch with no transistor or diode more scalable: molecular memories

scalable: molecular memories

Ä

Ä Continue MooreContinue Moore’’s Law beyond transistor ages Law beyond transistor age

y

y MultiMulti--layer memories have the potential to be lowest cost for layer memories have the potential to be lowest cost for litho defined memory

litho defined memory

Ä

Ä Drop below historical MooreDrop below historical Moore’’s Laws Law

y

y Seek and scan can be the lowest cost but involves new Seek and scan can be the lowest cost but involves new memory storage and sense mechanism

memory storage and sense mechanism

Ä

(26)

26

Sm a ll is not t ha t sm a ll

y

y XX--Y addressable memory is Y addressable memory is always limited by the limiting always limited by the limiting lithography steps: have to lithography steps: have to connect to the real world connect to the real world circuits

circuits

y

y Either self assembled circuits at Either self assembled circuits at the smaller geometry or new the smaller geometry or new innovative architecture

(27)

y

y Memory technologies requiring transistor switch will be Memory technologies requiring transistor switch will be limited in scaling

limited in scaling --> FeRAM, MRAM, diode switch scales > FeRAM, MRAM, diode switch scales better

better --> OUM, RRAM> OUM, RRAM

Ä

Ä Follows MooreFollows Moore’’s Law limited by transistor/diodes Law limited by transistor/diode

y

y Simple cross point switch with no transistor or diode Simple cross point switch with no transistor or diode more scalable: molecular memories

more scalable: molecular memories

Ä

Ä Continue MooreContinue Moore’’s Law beyond transistor ages Law beyond transistor age

y

y MultiMulti--layer memories have the potential to be lowest layer memories have the potential to be lowest

cost for litho defined memory

cost for litho defined memory

Ä

Ä Drop below historical MooreDrop below historical Moore’’s Laws Law

y

y Seek and scan can be the lowest cost but involves new Seek and scan can be the lowest cost but involves new memory storage and sense mechanism

memory storage and sense mechanism

Ä

(28)

28

M ult i-la ye r is sm a lle r

Level N+1: Antifuse, P-, P+, conductor, P+ (fill and antifuse made transparent) Matrix Confidential Level N+1: Antifuse, P-, P+, conductor, P+ (fill and antifuse made transparent) Matrix Confidential

Single Layer cell area =

Single Layer cell area =

4

4 λλ2

Multi Layer cell area =

4

4 λλ22_{/ N (number of}_{/ N (number of}

layers)

(29)

Bre a k ing t he sc a ling ba rrie r

y

y Memory technologies requiring transistor switch will be Memory technologies requiring transistor switch will be limited in scaling

limited in scaling --> FeRAM, MRAM, diode switch scales > FeRAM, MRAM, diode switch scales better

better --> OUM, RRAM> OUM, RRAM

Ä

Ä Follows MooreFollows Moore’’s Law limited by transistor/diodes Law limited by transistor/diode

y

y Simple cross point switch with no transistor or diode Simple cross point switch with no transistor or diode more scalable: molecular memories

more scalable: molecular memories

Ä

Ä Continue MooreContinue Moore’’s Law beyond transistor ages Law beyond transistor age

y

y MultiMulti--layer memories have the potential to be lowest layer memories have the potential to be lowest cost for litho defined memory

cost for litho defined memory

Ä

Ä Drop below historical MooreDrop below historical Moore’’s Laws Law

y

y Seek and scan can be the lowest cost but involves new Seek and scan can be the lowest cost but involves new

memory storage and sense mechanism

Ä

(30)

30

Se e k a nd Sc a n ha s be st sc a ling

pot e nt ia l

Se e k a nd Sc a n ha s be st sc a ling

pot e nt ia l

y

y With capability of contacting With capability of contacting areas smaller than X

areas smaller than X--Y cross Y cross points defined by lithography,

points defined by lithography,

very dense memory can be

realized

y

y The challenge is in the The challenge is in the development of multi

development of multi--probe probe systems as well as new

systems as well as new

memory mechanisms

y

(31)

One Winne r Only?

y

With the diverse requirement, NO one memory

technology can meet all the need

y

Market segment size tends to be an inverse function

of cost per bit => lower cost, larger market segment

y

There are special need that can only be met by

special memories

¾

¾ FeRAM, lowest power, contactless smartcardsFeRAM, lowest power, contactless smartcards

¾

¾ MRAM, fast read write, unlimited number of cycles_{MRAM, fast read write, unlimited number of cycles}

y

What is the killer

-

app that must have the new

memory? Otherwise, must compete on cost!

(32)

32

I nt e l Re se a rc h Ex a m ple s

y

When flash scaling slows down, ovonics

memory is our choice because of its projected

scaling capability and low cost

y

Ferroelectric polymer memory with multilayer

memory stacking has the potential to be very

low in cost

(33)

Ovonic s U nifie d M e m ory

Data Storage Region

Resistive Electrode Amorphous Chalcogenide Phase Change Material Heater Poly Crystalline y

y OperationOperation

y

y Chalcogenide material Chalcogenide material alloys used in re

alloys used in re-

-writable CDs and DVDs writable CDs and DVDs

y

y Electrical energy (heat) Electrical energy (heat) converts the material converts the material between crystalline between crystalline (conductive) and (conductive) and amorphous (resistive) amorphous (resistive) phases phases y

y Cell reads by Cell reads by

measuring resistance measuring resistance

y

y Non-Non-destructive readdestructive read

y

y ~10~101212 _{write/erase cycles}_{write/erase cycles}

y

y Medium write powerMedium write power

y

y Relatively easy Relatively easy

(34)

34

Fe rroe le c t ric Polym e r M e m ory

CMOS Base Wafer

Interface Logic Sense Amps/ Interconnect Charge Pump Charge Pump Word line Polymer Layer

Bit line Bit line Bit line

Polymer Layer Word line Word line Insulator (polymer) Word line Polymer Layer

Bit line Bit line Bit line

Polymer Layer Word line Word line dipole moment

y

Operation

y

y Polymeric Ferroelectric RAM Polymeric Ferroelectric RAM (PFRAM)

(PFRAM)

y

y Polymer chains with a dipole Polymer chains with a dipole moment

moment

y

y Data stored by changing the Data stored by changing the polarization of the polymer

polarization of the polymer

between metal lines

y

y Zero transistors per bit of storageZero transistors per bit of storage

y

(35)

Displa c e m e nt T im e line Ex a m ple

EPROM t o Fla sh

-Displa c e m e nt T im e line Ex a m ple

EPROM t o Fla sh

-1st _Product Availability

(36)

36

Whe n is t he Right T im e for

Disrupt ive T e c hnology I nse rt ion

Whe n is t he Right T im e for

Time Cost / Bit

(Log Scale) New

Memory

Initial Learning

NOW

Floating Gate Slow down

New Memory crosses over Floating Gate

(37)

Whe n is t he Right T im e for

Time Cost / Bit

(Log Scale)

New Memory

Initial Learning

NOW

Floating Gate Slow down

New Memory crosses over Floating Gate

(38)

38

Sum m a ry

y

NOR flash scaling will continue through innovation

with increasing difficulty

y

Multiple new memory technologies had been

evaluated and two promising candidates identified:

¾

¾ OUM for code and small data to replace NOROUM for code and small data to replace NOR

¾

¾ Polymer for low cost card memory to compete with NANDPolymer for low cost card memory to compete with NAND

y

The customers will ultimately decide which of the

new memory technologies will meet their need