Index of /intel-research/silicon

2003 IRPS

High Performance Logic

Technology and Reliability Challenges

Mark Bohr

Intel Senior Fellow

Outline

y

Logic Technology Evolution

y

90 nm Logic Technology

CPU Transistor Count Trend

1 billion transistor CPU by 2007

1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 1,000,000,000

1970 1980 1990 2000 2010

4004 8008 8080

8086 286 386TM CPU

486TM CPU Pentium® CPU

Pentium® II CPU Pentium® III CPU

Pentium® 4 CPU

CPU MHz Trend

10 GHz CPU by 2007

1 10 100 1,000 10,000

1970 1980 1990 2000 2010

MHz

8086

286 386TM CPU

486TM CPU

Pentium® CPU Pentium® II CPU

8080

Feature Size Trend

Feature Size

New technology generation introduced every 2 years

0.01 0.1 1 10

1970 1980 1990 2000 2010 2020

Feature Size Trend

Gate Length

Feature Size

Transistor gate length scaling faster for improved performance

0.01 0.1 1 10

1970 1980 1990 2000 2010 2020

CPU Power Trend

386

486

Pentium® CPU Pentium Pro®

CPU Pentium® II/II

CPU

Pentium® 4 CPU

1 10 100

1.5 1.0 0.8 0.5 0.35 0.25 0.18 0.13 0.09

Generation (um) Power

(W)

Logic Technology Evolution

Each new technology generation provides:

~

0.7x minimum feature size scaling

~ 2.0x increase in transistor density

~ 1.5x faster transistor switching speed

Reduced chip power

Outline

y

Logic Technology Evolution

y

90 nm Logic Technology

Key 90 nm Process Features

High Speed, Low Power Transistors

– 1.2 nm gate oxide

– 50 nm gate length

– Strained silicon technology

Faster, Denser Interconnects

– 7 copper layers

– New low-k dielectric

Lower Chip Cost

– 1.0 µm2 _{SRAM memory cell size}

90 nm Generation Transistor

50nm

W Contact

NiSi Layer

Silicon Gate Electrode

1.2 nm SiO₂ Gate Oxide

90 nm Generation Gate Oxide

Polysilicon Gate Electrode

Silicon Substrate

1.2 nm SiO₂

1.2 nm Gate Oxide Reliability

1.E+09

10 Years

T=110C

V_MAX=1.2V

1.E+08

1.E+07

1.E+06 TDDB

(sec)

1.E+05

1.E+04

1.E+03

1.E+02

5 6 7 8 9 10 11 12

(MV/cm) E_OX

Strained Silicon Transistors

Current Flow

Normal electron

flow

Faster electron

flow

Normal Silicon Lattice Strained Silicon Lattice

Transistor Performance Trend

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

1990 1995 2000 2005

Drive Current (mA/um) 1 10 Supply Voltage (V) NMOS PMOS 90 nm

90 nm Generation Interconnects

7 layers of copper interconnect

– 1 more layer than 0.13 µm generation

– Extra layer provides cost effective improvement in logic density

New low-k dielectric introduced to reduce wire-wire

capacitance

– Carbon-doped oxide (CDO) dielectric reduces capacitance by 18% compared to SiOF dielectric used on 0.13 µm

90 nm Generation Interconnects

pitch

M7 1080 nm

M6 720 nm

M5 480 nm

M4 400 nm

M3 320 nm

M2 320 nm

M1 220 nm

Low-k CDO Dielectric

Copper Interconnects

Cu + CDO Interconnects

Cu

Thin SiN layer

CDO K = 2.9

No trench

Void-Free Required for Electromigration

M1 M1 V1

V1

M1 M1 V1

Electromigration Enabling

Old process New process

Cu

CDO

Cu

CDO

Cu

CDO

Electromigration Improvement

Process 4 Process 3 1000 1000 100 100 10 10 1 1 9

999

9

955

9

900

8

800

7

700

6

600

5

500

4

400

3

300

2

200

1

100

5 5

1 1

Percent

First EM Process 1 Process 2

Ti

6-T SRAM Cell

y SRAM cell has area of 1.0 µm2

y Same process as high performance logic

y Small memory cell enables cost effective increase in CPU

performance by adding more on-die cache memory

Intel SRAM Cell Size Trend

90 nm

0.1 1 10 100

1990 1995 2000 2005

Cell Area

(um2)

per year

.71x

52 Mbit SRAM on 90 nm Process

10.1 mm

10.8 mm

330 million transistors on single chip

Initial 90 nm process certification vehicle

Same Process for Logic and SRAM

Logic

SRAM

• Microprocessors use same transistors and interconnects for Logic and SRAM

• On-die SRAM cache transistor count increasing for improved performance

52 Mbit SRAM Chips on 300 mm Wafer

Outline

y

Logic Technology Evolution

y

90 nm Logic Technology

Planar CMOS Transistor Scaling

Future

25 nm

15nm

Today

50 nm 30 nm 20 nm 15 nm Gate Length

R&D groups exploring aggressive scaling of conventional planar CMOS transistors

Transistor I

OFF

Leakage Trend

Production data Research data

in literature

Intel 15 nm transistor

(2001) Intel 30 nm transistor (2000) ( ) ( ) 1.E-04 1.E-06 1.E-08

I

_OFF (A/um) 1.E-10 1.E-12 1.E-14 10

Transistor Physical L_G (nm)

100 1000

• Transistor leakage current increasing as V_T scales

Fully Depleted Transistors

1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03

0 0.25 0.5 0.75 1 1.25

VG (Volts)

ID (A/ µ m ) DST Bulk Silicon VD= 1.3V

VD= 0.05V

Matched I_OFF

FD SOI 1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03

0 0.25 0.5 0.75 1 1.25

VG (Volts)

ID (A/ µ m ) DST Bulk Silicon VD= 1.3V

VD= 0.05V

Matched I_OFF

FD SOI

Source: Intel Components Research

L_G

T_Si

SiO₂

Fully-Depleted SOI (planar)

• FD SOI provides steeper sub-threshold slope, which can be used to reduce I_OFF or increase I_DSAT

Fully Depleted Transistors

W

_Si

L

_g

T

_Si

W

_Si

L

_g

T

_Si

Double-Gate (non-planar) Tri-Gate (non-planar)

Transistor I

GATE

Leakage Trend

0.001 0.01 0.1 1 10 100 1000

90 130 180 250 350 500

Technology Generation (nm)

I

_GATE

(A/cm2)

1 10

Tox (nm)

High-k Gate Dielectric

1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 1E-2 1E-1 1E+0 1E+1

0.50 1.00 1.50 2.00 2.50 3.00 3.50

Cox (µF/cm 2 ) J OX @ 1 V ( A /c m 2 ) SiO₂

Al₂O₃

HfO₂

ZrO₂ Ta2O5

Better

TiO₂

Source: Intel Components Research

Early Problems with High-K Dielectrics

-0.5 0 0.5 1 1.5

Gate Bias Ga te C a p a ci ta nc e 0 50 100 150 200 250 300 350 400 450 500

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

Eeff (MV/cm) E le c tr o n M o b il ity (c m 2 /V .s ) Universal Mobility Curve High-K SiO2

V_T instability due to charge traps Degraded inversion layer mobility

Interconnect Delay

Al + SiO₂

0.01 0.1 1 10

0.1 1 10

Interconnect Pitch (um) Interconnect

Delay (nsec)

10 mm Line

1 mm Line < 100 MHz

< 1 GHz

< 10 GHz

• Interconnect delay getting worse as pitch scales • Scaling line length helps keep delay constant

Narrow Line Width Resistivity Increase

0.5 1.0 1.5 2.0 2.5

0 100 200 300 400 500 Line Width (nm)

Cu Resistivity (normalized)

Cu resistivity increases for narrow lines due to: • Finite barrier layer thickness

Electromigration Requirements

Al Cu

1 10

65 90 130 180 250 350 500

Technology Generation (nm) Current

Density Requirement

(normalized)

• Current density increases ~1.5x per generation as feature size decreases and operating frequency increases

• EM improved on Al by adding alloy ingredients and shunt layers

Fragile Low-k Dielectric Materials

Si Chip

Organic

Package Solder

Bumps

• Low-k dielectric materials are mechanically weaker than SiO₂

• CTE mismatch between chip and package causes stress during chip bonding step

Summary

• High performance logic technology has scaled

at a rapid pace down to the 90 nm generation,

providing significant gains in density and

performance

• Going forward, transistor and interconnect

scaling challenges look formidable

For further information on Intel's silicon technology,

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