On-line Testing for Feedback Bridging Faults
4.2 Circuit modeling and FN-detector design using FSA frameworkFSA framework
4.2.1 Circuit modeling under bridging faults
The present subsection explains how sequential circuits having bridging faults are modeled as FSA. In most of the works on bridging faults, short is assumed between any two lines in the CUT. Ideally speaking, a bridging fault may involve any number of lines of a circuit, however, that would make the number of all possible faults exponentially high. So, in the widely accepted bridging fault models only two lines are assumed to be involved [17]. As per the fault model, the manifestation is in terms of logic AND and logic OR between the two lines. This fault model is called wired AND-OR fault model. In the CUT, the fault is represented once by adding an AND gate and then by adding an OR gate between the two lines involved in the fault. Henceforth in this chapter, the term fault will be used to refer to wired AND-OR bridging fault. Whenever, any other fault needs to be refereed to, it would be explicitly mentioned.
Fault is modeled as a part of the same FSA which is used to model the CUT under normal condition. To elaborate, the FSA is divided into sub-systems (i.e., a sub-set of states and transitions) and each sub-system is used to represent the CUT under a fault or normal condition. So, the variable setV is extended as V =S∪I∪C, where C is a set of k(= dlog2(p+ 1)e) status variables (normal or fault), wherepis the total number of possible faults in the CUT. S
x∈X
x(C) = {N, F1, F2,· · · , Fp}, where N stands for normal status and
Fi, 1≤i≤p, stands for theithfault status. The image x(C) ofC underxis called the fault label of the state x. The state mapping is modified as (S∪C)−→ {0,1}. It may be noted that status variables are dummy variables only used for modeling and are unmeasurable. It may be noted that if status variables are measurable then failure detection problem is trivial.
The occurrence of a fault (on the fly)Fi is captured by a transition from a statex1with x1(C) =N (in normal sub-system) to a state x2 with x2(C) =Fi (in Fi sub-system). For a fault Fi such a transition is called si-transition (i.e., start of fault Fi) and is represented as si = hx1, T, x2i, where x1(C) = N, x2(C) = Fi. Firing of an si-transition does not depend on input variables, rather it is “T” implying “always true”. Due to occurrence of an si- transition, only the status variable changes its value fromN toFi and all the other variables remain unchanged. Thus, si-transitions are unmeasurable. In synchronous circuits the state register changes only at the triggering edges of the clock depending upon the inputs. So, even if faults occur on the fly (in the NSF block) their effects are not manifested before the next active clock edge when the circuit moves to a state that is different from the normal condition. 1
Now we repeat the definitions of some terminologies in brief which are related to the FSA modelG. The detailed about the definitions can be found in Chapter 3, Section 3.2.
Definition 4.1. N-state and Fi-state: AG-state is called normal (i.e.,N-state), denoted as x0j, j ≥1, if x0j(C) = N. The set of all normal states is denoted as XN.
A G-state is called an Fi-state, denoted as xil, l≥1, if xil(C) = Fi. The set of all Fi states is denoted as XFi.
Definition 4.2. Normal G-transition and Faulty G-transition: A G-transition hx, σ, x+i is called a Normal (FaultyFi)G-transition if x, x+∈XN(XFi).
Definition 4.3. Measurement equivalent states: Two statesx1 andx2 are measurement equivalent, denoted as x1Ex2, if x1|S =x2|S; x1|S denotes the projection (i.e., values) of the state variables in S.
Definition 4.4. Measurement equivalence transitions: Two transitionsτ1 =hx1, σ1, x+1i and τ2 =hx2, σ2, x+2i are measurement equivalent, denoted as τ1Eτ2, if x1|S =x2|S, x+1|S = x+2|S and σ1|I =σ2|I.
1For explanation of our proposed OLT scheme we consider faults only in the NSF block. A bridging fault in the flip-flops can be represented using a bridging fault involving the input and output lines of the NSF block. It may be noted from Figure 3.1 that outputs and (secondary) inputs of NSF block are input lines and output lines respectively, of the flip-flops.
D−FF
D−FF
v1
v2 Primary
input v3
v1
v2 v1+=v1’v2+v2’v3
v2+=v1’v2’+v2v3
Clock e1
e2
Figure 4.1: A simple sequential circuit.
D−FF
D−FF v1
v2 Primary
input v3
v1
v2
Clock e1
e2
Bridging (e1,e2)
v1+=v1v2’v3+v1’v2
v2+=v1’+v2 e1
e2*
*
Figure 4.2: Sequential circuit with AND-bridging between linese1 ande2.
In this work, we have taken a simple sequential circuit, shown in Figure 4.1, for illustration of the theory. We assume a wired AND-bridging fault (denoted as F1) between lines e1 and e2, as shown in Figure 4.2. The lines marked e∗1 and e∗2 represent the values of lines e1 and e2 under the fault. All possible values ate1e2 are 00,01,10,11. Among all these four possibilities, 00 and 11 do not lead to any difference in logic values at any net in the circuit under fault condition compared to the normal condition. However, if e1e2 = 01 then e∗1e∗1 = 00 and if e1e2 = 10 then e∗1e∗1 = 00. So, the wired AND-bridging fault between two lines e1 and e2 is active only when these lines have different logic values. When e1e2 = 01, then fault is manifested through only linee∗2, becausee1 =e∗1 = 0 (i.e., there is no change in e∗1 compared toe1 under fault) however,e2 = 1 6=e∗2 = 0 (i.e., there is change ine∗1compared to e1 under fault). In a similar way, when e1e2 = 10, then fault is manifested through only line e∗1. So, it can be stated that in wired AND-bridging fault the line which has the logic value 0 (e.g., e2 when e1e2 = 10) is “dominating” over the line, called “dominated” (e.g.,e1 when e1e2 = 10), which has the value 1. In other words, in wired AND-bridging fault the logic value at the dominating line is 0 which overrides the value at the dominated line by pulling it from 1 to 0. This implies that wired AND-bridging fault results in s-a-0 fault at the dominated line when the dominating line has the value 0.
Thus, test patterns for detecting the wired AND-bridging fault between linese1 ande2 involve the following steps:
• All input patterns which result in e1 = 0 (dominating) and detect s-a-0 fault at e2 (dominated), by propagating the fault effect at an output. This is illustrated in Figure 4.3(a).
• All input patterns which result in e2 = 0 (dominating) and detect s-a-0 fault at e1 (dominated), by propagating the fault effect at an output. See Figure 4.3(b).
Note: In this chapter we will limit our discussion only on wired AND-bridging fault.
The mechanism for AND-bridging fault can be directly applied for OR-bridging fault by applying the duality principle. For example, in case of OR-bridging thedominating line has a value of 1 and it pulls the dominated line from 0 to 1, i.e., a s-a-1 fault.
As shown in Figure 4.1, under normal condition the expressions for the NSF block outputs arev1+ =v01v2+v20v3 andv2+=v01v20+v2v3. The presence of the bridging fault changes the output expressions tov+1 =v1v02v3+v01v2 and v2+=v01+v2 (Figure 4.2). Figure 4.4 shows the FSA model for the normal and faulty behavior of the circuit. In the circuit modeling, states for the normal submachine will be designated asx0j, 1 ≤j, and those of the ith fault (i.e.,Fi-submachine) are designated asxij, 1 ≤j; likewise for the transitions. In this example
D−FF
D−FF
v1
v2 Primary
input v3
v1
v2
Clock
e2
v1+
v2+ e1
s−a−0 at e2 0
(a) AND-bridging wheree1 dominates e2.
D−FF
D−FF
v1
v2 Primary
input v3
v1
v2
Clock e1
v1+
v2+ e2
s−a−0 at e1
0
(b) AND-bridging wheree2dominatese1.
Figure 4.3: AND-bridging fault
as there is a single fault denoted asF1, the faulty states and transitions are designated asx1j, 1≤j and τ1j, 1≤j, respectively. The occurrence of the fault is captured by the transitions markeds1.
00
01
10
11
00
01
10
11 τ01:0
τ03:0 τ04:1
τ τ
τ07:0 τ02:1
τ08:1
τ11:0 τ :1
13:0 τ
12
τ14:1
τ18:1 τ17:0 τ15:0
16:1
X01 X11
X02 X12
X03 X13
X04 X14
τ
<v1,v2>
Transition label
Transition enabling condition (value of input variable)
values of state variables
State label 05:0
06:1
FSA for Normal Circuit Status variable: N
FSA for Circuit with Bridging Fault Status variable: F
s1
s1
s1
s1
1
Figure 4.4: FSA model for the circuit (of Figure 4.1) under normal and faulty condition
Now comparing the transitions under normal condition with the corresponding ones after the bridging fault in the FSA model given in Figure 4.4, it is noted that there are three transitions that reflect a change in behavior after bridging fault. These transitions are τ12 : hx11,1, x12i, τ13 : hx12,0, x14i and τ17 : hx14,0, x12i. This is because, for transition τ12:hx11,1, x12i the corresponding transition in normal condition is τ02 :hx02,1, x04i, where x01|S = x11|S = 00, σ02 = σ12 = 1 but x04|S(= 11) 6= x12|S(= 01). In simple words, in these three transitions, for a given state and input variable combination the values of the state variables in the next state are different in the normal model compared to its faulty counter part. Such transitions that result in manifestation of faults are termed as F D- transitions (i.e., Fault Detecting transitions). All other transitions in the normal model have an equivalent counterpart in the faulty model; e.g., τ01Eτ11 because, τ01 :hx01,0, x02i, τ11:hx11,0, x12i and x01|S =x11|S = 00, σ01=σ11= 0, x02|S =x12|S = 01.
D−FF
D−FF v1
v2 Primary
input v3
v1
v2
Clock e1
e2
v1+
v2+ 1/0
1/0 1/0
(s−a−0 at e1)
=0
=0
=1
e2) (driving 0 to
0 1
0
1
1
Figure 4.5: F D-transitionτ12 = h00,1,01i detects the given AND-bridging fault by driving 0 to linee2 and checkings-a-0 fault at line e1.
Now we show using the example of an F D-transition (τ12 =h00,1,01i say), that leads to driving 0 at thedominatingline and detects a s-a-0 fault at thedominatedline. As shown in Figure 4.5, τ12 = h00,1,01i implies that v1 = 0, v2 = 0, v3 = 1, which results in 0 at e2 and 1 ate1. Since we need to detect a s-a-0 fault at e1, applying 1 sensitizes the fault; this is marked as “1/0” in e1 in Figure 4.5, which implies that under normal condition value of the line is 1 and under the s-a-0 fault it becomes 0. It can be easily verified from the figure that v1 = 0, v2 = 0, v3 = 1 also propagates the fault effect (i.e., 1/0) to the NSF outputv1+, leading to its detection. Similar can be shown for the other two F D-transitions.