On-line Testing at Register Transfer Level
5.5 Experimental evaluation
To show the feasibility of the proposed OLT scheme, we have selected different benchmark circuits. The benchmark circuits include Greatest Common Divisor (GCD), Sum of squares (sosq), 8-bit multiplier (mult8X8) and Differential equation (diffeq). These circuits have been taken from the HLSynth92 academic benchmark suit [1]. For each benchmark circuit, its RTL model is constructed from its behavioral description which is written in VHDL.
Then data path of the RTL circuit is partitioned into a number of cones with respect to the registers. Appropriate high level fault models [18,25,46,59] have been chosen and applied into the different modules of the RTL data path. Using the HLDD based techniques discussed in the last two sections, we have generated the exhaustive set of F D-control-patterns for detecting faults at different modules and finally designed the F N-detector circuit using these F D-control-patterns.
The formulas for calculation of the performance parameters are as follows.
Fault Coverage(FC): F C = N umber of f aults covered
T otal number of f aults ×100%
Area Overhead(AO): AO= Area of F N−detector af ter synthesis Area of the CU T
Detection latency(DL): For a fault Fi, DL = (dnf di/mf die)− 1, where nf di be the total number of F D-control-patterns for Fi and among them,mf di number of F D-control- patterns is considered in construction of the F N-detector.
5.5.1 Fault coverage analysis
Table 5.3 shows the details about RTL fault coverage and gate level stuck-at (s-a) fault coverage [36] [12] for different benchmark circuits. We have calculated the fault coverage with
0 detection latency, i.e., all theF D-control-patterns for each covered fault are considered in the construction of the F N-detector. Column 1 shows the name of the benchmark circuits, Column 2 shows the number of all possible RTL faults, Column 3 shows the percentage of coverage of the RTL faults. An RTL fault is not covered implies, we could not generate any F D-control-pattern for that fault. Column 4 shows the time required for the generation of the exhaustive set of F D-control-patterns. Column 5 shows the number of gate level s-a faults. Column 6 and Column 7 represent s-a fault coverage for the OLT scheme reported in [36] and [12], respectively. Column 8 and Column 9 represent the time taken for generation of the exhaustive set of test patterns for [36] and [12], respectively. The scheme reported in [36] works successfully only for small sized circuits because they have used FSM for circuit modeling, whereas the scheme reported in [12] is more scalable compared to [36] because of the use of OBDD.
Table 5.3: Fault coverage and exhaustive test set generation time of the proposed method and comparison with existing methods [36] and [12]
Circuit RTL fault coverage and Time in seconds∗ Gate level fault coverage and Time in seconds∗
#Faults Fault coverage(%) Time # Faults Fault coverage(%) Time
[36] [12] [36]∗∗ [12]
GCD 19 89.47 56 844 92 93 NA 270
sosq 31 87.1 128 1938 88 87 NA 724
mult8X8 39 84.6 304 3915 NA 92 NA 1680
diffeq 46 95.65 823 15836 NA 95 NA 9876
∗Executed in AMD Phenom IIX3 710 Processor with 4 GB RAM in Linux OS.
∗∗ [36] has not reported the execution time for test pattern generation
The fault coverage of the proposed scheme and the existing schemes ( [36] and [12]) are almost same but the time taken to generate theF D-control-patterns is much lower than the time taken to generate the test patterns in [36] and [12]. The reason is that the proposed scheme generates F D-control-patterns at RTL whereas the existing schemes generate test patterns at gate level and the number of RTL faults of a circuit is less compared to s-a faults at gate level. It has been found that there exists close proximity between RTL and gate level faults [25, 59, 92]. Thus, the F D-control-patterns generated at RTL have good correlation with gate level test patterns. So there is no compromise in quality of testing at RTL . Further, the number ofF D-control-patterns at RTL is less than that of test patterns at gate level for a circuit, thus, the proposed scheme has good impact on minimization of area overhead. In next subsection we will discuss the area overhead of the on-line tester in detail.
5.5.2 Area overhead analysis
Table 5.4 shows the area overhead of the F N-detector for different benchmark circuits with different values of detection latency. Column 1 of the table shows the name of the benchmark circuits. Column 2 shows the area overhead of the proposed scheme when detection latency is equal to 0. Columns 3 and 4 show the area overheads of the schemes reported in [36] and [12], respectively, when detection latency is equal to 0. Similarly, Columns 5, 6 and 7 show the area overheads when the detection latency is equal to 3 and Columns 8, 9 and 10 show the area overheads when the detection latency is equal to 5. The following points may be noted.
Table 5.4: Area overhead of the proposed method and comparison with [36] and [12]
Circuit Area overhead for different values of detection latency
For detection latency=0 For detection latency= 3 For detection latency=5 Proposed Existing Proposed Existing Proposed Existing
scheme schemes scheme schemes scheme schemes
[36] [12] [36] [12] [36] [12]
GCD 0.97 2.4 2.34 0.93 2.2 2.25 0.88 2.1 2.08
sosq 0.92 1.65 1.67 0.90 1.52 1.48 0.86 1.3 1.23
mult8X8 0.83 NA 1.23 0.78 NA 0.95 0.63 NA 0.91
diffeq 0.74 NA 1.14 0.68 NA 0.92 0.57 NA 0.88
• Increase in the detection latency results in reduction of the area overhead of the F N- detector. For example, the area overhead of the proposed scheme for the circuit diffeq is 0.74 with 0 detection latency. The area overhead reduces to 0.68 when the detection latency increases to 3 and it reduces further to 0.57 when the detection latency increases to 5.
• For a given detection latency, the area overhead of the proposed scheme is always less compared to [36] and [12]. This is because the proposed scheme designs the on-line tester circuit using the F D-control-patterns which are generated at RTL, whereas the schemes in [36] and [12] designed the tester circuits using the test patterns which are generated at the gate level. To elaborate, since the the number of RTL faults of a circuit is less than that of gate level faults (s-a faults), the number of F D-control-patterns generated at RTL for a circuit is also less than that of test patterns generated at the gate level. It implies less number ofF D-control-patterns in theF N-detector corresponding
to the RTL based representation, which results less area overhead compared to gate level testing.
• In RTL, we can decide the invalid F D-control-patterns for a fault and drop them in the design of the F N-detector circuit, thus the area overhead can be further reduced.
Whereas, in the case of gate level circuits there is no such feature to decide invalid test patterns for a fault. So, in the gate level case, we include all the test patterns for a fault in on-line tester design which increases the area overhead.