6.1 Introduction
Since the last two decades synchronous circuits have widespread use in VLSI design whereas asynchronous circuits have not been used in practice to that extent. However, compared to synchronous circuits, asynchronous circuits promise a number of advantages such as no clock skew problem, higher degree of modularity, low power consumption and average case performances rather than worst case executions [111]. In recent years, the use of the asynchronous circuits in the semiconductor industry has matured a lot because of the above advantages. Testing of asynchronous circuits as compared to synchronous circuits is considered difficult due to the absence of the global clock [50]. Also, On-line Testing (OLT) of such circuits is one of the challenging tasks. It is seen that most of the OLT schemes have been designed for synchronous circuits only. There are very few works that have been proposed on OLT of asynchronous circuits [107, 109, 129]. The details about these schemes can be found in Chapter 2, Subsection 2.3.4. The scheme proposed in [129] is based on traditional full replication technique, thus, it leads to more than 100% area and power overheads. The works reported in [107, 109] are based on checking of a predefined protocol using Mutex elements. So, these schemes are protocol specific and use of Mutex elements make area overhead of these techniques high.
In this chapter, we aim at developing an efficient OLT scheme for asynchronous circuits which is protocol independent and incurs low area overhead. The proposed non-intrusive OLT scheme is easily applicable to all type of Speed Independent asynchronous circuits (SI circuits). The scheme starts with modeling of SI circuits along with their faults using Signal
Transition Graphs (STGs), then translating them into State Graphs (SGs), from which Fault Detecting transitions (F D-transitions) are generated. In case of OLT of synchronous circuits, the on-line tester circuit is a Finite State Machine (FSM) which detects the occurrence ofF D- transitions (the procedure is discussed in Chapters 3 and Chapter 4). A synchronous circuit can be synthesized in a straightforward manner from the FSM specification that performs on- line testing. In similar way a synchronous circuit can be synthesized as the on-line tester for OLT of an asynchronous circuit, but the use of synchronous circuit for OLT of asynchronous circuit is not desirable. So, we propose a new technique for design of on-line tester, called Fault versus Normal condition detector (F N-detector), which can be synthesized as an SI circuit. The tester is designed as state graph model which is live and has Complete State Coding (CSC); these properties ensure its synthesizability as an SI circuit. Finally, we discuss the procedure of generation of F D-transitions in an efficient manner directly from the circuit description using Ordered Binary Decision Diagram (OBDD), without explicitly constructing the SG models whose complexity may be prohibitively high for large circuits.
The chapter is organized as follows. In Section 6.2, we discuss the modeling of an SI circuit using STG under normal and faulty conditions. Following that, conversion of STGs into SGs and generation of F D-transitions are discussed. In Section 6.3, we illustrate the design of the F N-detector using F D-transitions. Efficient generation of F D-transitions using OBDD is discussed in Section 6.4. Section 6.5 presents experimental results regarding area overhead and fault coverage of the F N-detector. Also, comparison of area overhead of the proposed scheme with other similar techniques is reported. Finally, we conclude in Section 6.6.
6.2 SI circuit modeling using Signal Transition Graph and generation of F D-transitions
In this section, we start with modeling of an SI circuit using STG under normal and faulty conditions, then convert the STGs into SGs and generateF D-transitions. Just like modeling of synchronous circuits discussed in Chapter 3 and Chapter 4, the basic FSA framework is also used to model asynchronous circuits with slight modification. In case of synchronous circuits, state changes in the FSA occur only at the active edge of the register clock, irrespective of the time of changes in the inputs. On the other hand, in asynchronous circuits, state changes can occur immediately after a transition in the inputs. FSA used to model an asynchronous circuit is called an AFSA (Asynchronous FSA) [80]. An alternative to AFSA is Burst-mode (BM) state machines [80]. BM state machine and AFSA are similar
from the modeling perspective, however in case of the former, transitions are labeled with signal changes rather than their explicit values, which is the case in AFSAs. AFSAs and BM state machines assume that inputs change first followed by outputs and finally a new state is reached. Due to the strict sequence of signal changes all asynchronous protocols cannot be modeled using AFSAs or BM state machines. Petri net (PN) is widely accepted modeling framework for highly concurrent systems [27]. PN models a system using interface behaviors which are represented by allowed sequence of transitions or traces. The view of an asynchronous circuit as a concurrent system makes PN based models more appropriate than AFSAs and BM state machines for their analysis and synthesis. There are several variants of PNs among which Signal Transition Graph (STG) is generally used to model asynchronous circuits. The major reason is that the STG interprets transitions as signal transitions and specifies circuit behavior by defining casual relations among these signal transitions [71].
The SI circuit shown in Figure 6.1 (taken from [71]) will be considered as Circuit Under Test (CUT) to illustrate our proposed scheme. Traditionally synchronous circuits consist of blocks of combinational logic connected with clocked latches or registers, while in case of SI circuit designs, we basically have logic gates as building blocks with C-elements, which act as storage elements. Transistor level diagram of C-element is shown in Figure 6.2; logic function of the C-element can be described by the Boolean equationC =AB+AC0+BC0, where C is the next state and C0 is the old state value [71, 106]. The output of C-element becomes logically high (low) when both the inputs are logically high (low), otherwise it keeps its previous logic value. There are two types of C-elements that are used in SI circuits;
static C-element and dynamic C-element. The static version of C-element promises that the information inside it can be stored for unbounded periods. However, dynamic version of C-element provides gains in terms of area, power and delay [77, 105, 106, 120]. Since circuits having high operating speed, low area and power consumption are preferred in modern days, we have chosen SI circuits with dynamic C-elements instead of static ones.
Figure 6.3 shows the STG for the CUT being considered. Rising (falling) transitions on signals, indicated by +(−), are shown in the STG. The dark circles along the arcs are called tokens. A token indicates one of possibly a set of signals that enable a transition to fire.
If all input arcs for a signal transition have tokens then that signal transition is said to be enabled. For example, when signalRin goes high (denoted by Rin+) and signalRout goes high (denoted by Rout+), only then Aout+ transition can take place. Upon firing Aout+, a token is placed on each of its outgoing arcs, thus enabling Rin−. Note that Rout− is enabled afterAout+ and Ain+.
In this work we have considered SI circuits that contain C-elements (we assumed