Introduction
1.3 Motivations and Contributions of the thesis
Based on the literature review on OLT of digital circuits (in Section 1.1) and application of DDs in circuit testing (in Section 1.2), the contributions of the thesis are presented in this section. In addition, motivations of the proposed works are also discussed.
• Flexible OLT scheme design: An OBDD based approach to OLT of digital VLSI circuits with measurement limitation
– Since the on-line tester circuit is fabricated on the same chip with the CUT, thus any point of the CUT can be tapped (measured) easily. This enables the measurement of any required digital parameter of the CUT by the tester. So all of the above mentioned OLT schemes have ignored the issue of tap points or measurement limitation [12, 13, 35, 36]. However, tapping of lines of any circuit results in increase of load (fan-outs) on the gates which drive the tap points.
To handle the increased load extra buffers are required, which increase the area of the circuit. If the on-line tester is designed with high number of tapings in the CUT, it results in huge area overhead. So, minimization of tap points (i.e, measurement limitation) of the CUT by the tester is another parameter which needs to be studied from the OLT perspective.
– In this contribution, we design an OBDD based OLT scheme for digital circuits, targeting minimization of tap points. However, minimization of tap points also compromises fault coverage and detection latency. We have considered “number of tap points” as a new design parameter to provide flexibility in terms of trade-offs between area overhead versus fault coverage and detection latency. The scheme starts with generation of test patterns for all possible faults of the circuit under full measurement. Following that, the test patterns that can still detect faults under a given measurement condition are retained. Finally, the on-line tester is designed using these remaining test patterns. The procedure of generation of test patterns and determination of test patterns under measurement limitation are implemented using OBDDs.
– Results on ISCAS’89 benchmark circuits illustrate that measurement limitation has minimal impact on fault coverage and detection latency but reduces the area overhead of the tester. Further, it was also found that for a given detection latency and fault coverage, area overhead of the proposed scheme is lower compared to other similar schemes reported in the literature.
• OLT for advanced fault model: An OBDD based approach to OLT of digital VLSI circuits for feedback bridging faults
– In majority of the works on OLT of digital circuits, single s-a fault model is considered. However, in modern integration technology, single s-a fault model can capture only a small fraction of real defects [135] and as a remedy, advanced fault models such as bridging faults, transition faults, delay faults, etc., are now being considered. The number of OLT schemes for advanced fault models is few and most of them are based on the bridging fault model. Since feedback bridging faults may cause oscillations, so detecting them on-line is a difficult task in OLT. Most of the works on OLT of bridging fault model have considered only non-feedback bridging faults and ignored feedback bridging faults. As the existing schemes have directly dropped all the feedback bridging faults, thus these schemes compromise fault coverage significantly [13, 73]. However, not all feedback bridging faults create oscillations and even if some does, there are also test patterns for which the fault effect can be manifested logically. Thus, there is a need to study the importance of non-oscillating feedback bridging faults in OLT.
– In this contribution, we design an OBDD based OLT scheme for bridging fault model. The proposed scheme considers both non-feedback and feedback bridging
faults. The major steps of the scheme are−(a) checking if a feedback bridging fault causes oscillations and filtering out oscillating feedback bridging faults, (b) generating exhaustive test patterns for non-feedback bridging faults and non- oscillating feedback bridging faults. All these steps are implemented using OBDDs which enable the proposed scheme to handle fairly complex circuits.
– Results on ISCAS’89 benchmarks illustrate that consideration of feedback bridging faults along with non-feedback ones improve fault coverage, however, increase in area overhead is marginal compared to schemes only involving non- feedback faults.
• OLT for circuits at higher description level: A HLDD based approach to OLT of digital VLSI circuits at Register Transfer Level
– Most of the OLT schemes reported in the literature are at the gate level and these techniques take reasonable computational time and are not scalable for larger circuits. The major reason being these schemes work at bit level, leading to the state explosion problem. This issue of scalability can be solved by developing OLT schemes for circuits at higher description levels, like RTL, behavioral level, etc.
The number of OLT schemes at higher description level is less compared to gate level [43, 57, 58] and they have major issues such as high latency, intrusiveness, architecture dependency, etc. Thus, there is a need to develop efficient OLT schemes at RTL in order to overcome these issues.
– The partial replication based OLT schemes at gate level using OBDDs [12, 13]
satisfy almost all efficient parameters of OLT, i.e., non-intrusiveness, architecture independence, low area and power overheads, low detection latency, etc. However, these schemes are not scalable to handle large circuits because they work at gate level and the test pattern generation time of these schemes are quite high even for moderate sized circuits. To retain the advantages of partial replication based schemes, in this contribution we aim at developing a partial replication based OLT scheme at RTL. However, unlike the use of BDD for gate level representation, in RTL we use HLDD. The CUT is partitioned into a number of sub-circuits and each sub-circuit is represented using different HLDDs under normal and faulty conditions. For each fault, Fault Detecting control patterns (F D-control- patterns) are generated from HLDD representations. Finally, on-line tester circuit is designed usingF D-control-patterns and their faulty responses.
– The proposed scheme is applied to different HLSynth92 benchmark circuits and
it is shown that the test generation time is greatly improved using HLDDs, thus, large circuits can be easily handled. It also achieves comparable fault coverage and area overhead with respect to OLT schemes at gate level.
• OLT for asynchronous circuits: An OBDD based approach to OLT of Speed Independent asynchronous circuits
– Recently, VLSI community has grown interest in asynchronous circuits because they have no clock skew problem, have potentially lower power consumption, can be designed for average case performances rather than the worst case performances, and have higher degree of modularity. Testing of asynchronous circuits as compared to synchronous circuits is considered difficult due to the absence of the global clock. Also, OLT of such circuits is one of the challenging tasks. It is seen that most of the OLT schemes are designed for synchronous circuits compared to asynchronous circuits. There are very few works that have been proposed for OLT of asynchronous circuits [107, 109, 129] and are based on Mutex approach. However, these schemes have issues like high area overhead, protocol dependency, etc. Thus, there is a need to develop efficient OLT schemes for asynchronous circuits to overcome these problems.
– In this contribution, we propose an OBDD based OLT scheme for Speed Independent asynchronous (SI) circuits which is protocol independent and incurs low area overhead. We model the SI circuits along with their faults as Signal Transition Graphs (STGs) and then translate them into State Graphs (SGs), from which test patterns are determined. An efficient way of generation of the test patterns directly from the circuit description using OBDD, without need of the explicit SG model, is also discussed. Finally, we propose a new technique for on-line tester design which can be synthesized as an SI circuit. The tester is designed as SG model which is live and has Complete State Coding (CSC); these properties ensure its synthesizability as an SI circuit.
– The scheme is applied to different SI benchmark circuits and it is found that the area overhead for the on-line tester is much less compared to the existing Mutex approach. The scheme provides flexibility to trade-off area overhead by reducing fault coverage and detection latency depending upon the testability requirements.
Such flexibility can not be achieved by the Mutex approach.