Structural vs. functional testing

Literature review: On-line Testing of Digital VLSI Circuits and Decision

2.1 Digital VLSI testing

2.1.1 Structural vs. functional testing

The tests used for verifying that the chip meets the input-output specifications are called functional testing. Typically they have low fault coverage. Further, test pattern generation for exhaustive functional testing may be quite expensive. The number of test vectors required for this is of the order of 2ⁿ, where n is the number of inputs. The situation becomes more complex if it has sequential elements in it [2,17]. For example, the 32-bit full adder shown in Figure 2.3 requires 2³³ vectors for exhaustive functional testing. Using structural knowledge of the system this complexity, however, can be reduced to a great extent. Structural testing, introduced by Eldred in [38], depends on the specific structure of the circuit involving gate types, interconnects, fault models, etc. One of the advantages of structural testing is the ability to develop efficient algorithms to generate the structural test vectors. For example, by using the information about the structure of the adder (shown in Figure 2.3) and adding a small amount of additional hardware, it can be tested with 8 test vectors only. The 32 bit adder with DFT circuitry is shown in Figure 2.4.

It may be noted that in this case, two−31 bit shift registers, and 31 number of 2 : 1 multiplexers comprise the additional DFT circuit. One shift register (called input register) provides inputs to the “carry input” bits of the individual adders during test and the other shift register (called output register) latches outputs from the “carry output” bits of the individual adders. In the modified 32 bit adder, the carry input to the i^th (full) adder is multiplexed with the i^th bit of the input shift register, 1≤i≤31. During normal operation

Table 2.1: Variants of VLSI testing

Criterion Attributes of testing

method

Terminology

When is the test per- formed?

Concurrently with the normal system operation

On-line/Concurrent testing

As a separate activity Off-line testing Where is the source of

stimuli?

Inputs during operation On-line testing

Within the chip Built-In-Self-Test (BIST) Applied by an external device Automatic Test Equipment

(ATE) based testing

What is tested? Design errors Design verification testing

Fabrication errors Manufacturing test Failure during operation On-line testing (OLT) Which physical object

is being tested?

Wafer Non packaged ICs level testing

IC Packaged level testing

Board Board level testing

System System level testing

How are the stimuli ap- plied?

In a fixed predetermined order Static Testing

Depending on results Adaptive testing How fast are the stim-

uli applied?

Much slower than the normal speed of operation

DC (static) testing

At normal speed of operation At-speed testing Who checks the re-

sults?

On-chip circuit Self-checking

External tester External testing

A0 B0 A1 B1 A30 B30 A31 B31

C0

C1 C2 C31

0^th Full adder

1^st 30^th 31^st

Full adder Full adder Full adder

S0 S1 S30 S31 C_out

Figure 2.3: A 32 bit ripple carry adder

1 31

1 31

A0 B0 A1 B1 A31 B31

C0 0^th

Full adder

1^st 31^st

Full adder Mux 31 Full adder

Mux 1

C1 C2 C31

S0 S1 S31 Cout

of carry) Register data out (DFT for observability

Test control

Register data in ( DFT for

controllability of carry )

Figure 2.4: A 32 bit ripple carry adder with the DFT circuitry

of the 32 bit adder, the multiplexers connect the carry input of the i^th (full) adder to the carry output of the (i−1)^th (full) adder, 1≤i≤31. However, during test, the multiplexers connect the carry input of the i^th (full) adder to the output of the i^th bit of the input shift register, 1≤i≤31. The values in the shift register are fed externally. It may be noted that by this DFT arrangement all the (full) adders can be controlled individually as direct access is provided to the carry inputs of the adders; inputs other than carry are already controllable.

Hence, testing in this case would be for each (full) adder individually and that requires 8 test vectors as each of the 32 full adders can be tested in parallel. Correct operations of each of the full adders are determined by looking at the sum and the carry outputs. Sum outputs are already available externally and hence no DFT circuit is required to make them directly observable. For the carry outputs, however, another similar DFT arrangement is required to make them observable externally. This would require the output (31 bit parallel load and) shift register where the carry output bit of the (i−1)^th adder is connected to thei^th input of the output shift register, 1≤i≤31. Once the values of all the carry bits are latched in the register, which is done in parallel during test, they are shifted out sequentially. In this case a full adder is tested functionally and structural information is used at the cascade level.

Thus, it may be stated that “structural testing is functional testing at a level lower than the basic input-output functionality of the system”. In the case of digital circuits, structural testing is “functional testing at the level of gates and flip-flops”. Structural test vectors aim to detect manufacturing faults and try to confirm the correctness of the device structures in the manufacturing process like wires, flip-flops and gates. The pros and cons of structural and functional testing are shown in Table 2.2.