Literature review: On-line Testing of Digital VLSI Circuits and Decision
2.2 Literature review: On-line testing of digital VLSI circuitscircuits
2.2.2 Self-checking design using error detecting codes
function Next state
Output logic
State register
MISR
logic Reference
signal
Comparator PO
PI
Status
FSM for the circuit Signature monitor
Comparison
Figure 2.7: Basic architecture for signature monitoring
state assignment procedure of the FSM may have to be modified to take into account the constraints related to such an invariance. In other words, signature monitoring techniques for OLT require some special properties in the circuit structure, so they require re-synthesis and re-design, which lead to a change in the original structure of the circuit; they are accordingly termed as intrusive OLT methodologies. In the worst case, when the FSM graph is well connected, a large number of new states are added to achieve the signature invariant properly. Further, the state explosion problem in FSM makes the application of this scheme difficult for practical circuits; results reported in the OLT literature using these schemes are limited to circuits having typically about one hundred states.
parity off(i), 1’s count in f(i), etc. The basic self-checking design scheme discussed above is depicted in Figure 2.8.
CUT function f
characteristic predictor
Output
PO
Error Predicted
output characteristic
Checker
indication PI
i
Figure 2.8: Basic architecture for self-checking circuit
The technique of OLT using self-checking circuits based on error detecting codes was motivated from the error detection and correction techniques used in communication. The CUT output (or information) bits are augmented with some additional bits, called check bits (using an additional logic), such that under normal condition of the CUT and the additional logic, the CUT output augmented with the check bits is a code word of the error detecting code chosen. The checker verifies whether the CUT output augmented with the check bits is a code word of the error detecting code chosen. The effect of a fault in the CUT leading to change in some output bit is called an error. The above mentioned technique can be easily used for sequential circuits [53, 118] where the CUT illustrated in Figure 2.8 is the next state function of the sequential circuit. The circuit corresponding to the output characteristic predictor feeds additional flip-flops (other than the ones in the original circuit).
Thus, the outputs of circuit flip-flops augmented with that of the additional flip-flops is a code word of the error detecting code chosen. The checker taps the outputs of these flip-flops taken together. The basic self-checking design scheme for sequential circuits is depicted in Figure 2.9.
Before we move on to presenting the most important error detecting codes, we define some fundamental terms used in the context of self-checking circuits; they can be found in almost every publication addressing self-checking designs [14, 53].
Self-testing circuit: A circuit is self-testing, if for every fault in the specified fault model, there is an input that produces a non-code output.
Fault-secure circuits: A circuit is fault-secure, if an input can produce a non-code word or a correct code word. That is, they cannot be incorrect code words.
Totally Self-Checking (TSC): A circuit is TSC with respect to all the modeled faults if and only if it is both self-testing and fault-secure.
Output function block
(Output function block) Output characteristic predictor
Checker
(Output function block)
Next state function f
Output characteristic (Next state function block)
predictor
(of the circuit) Flip−flops
Flip−flops (augmented)
Checker (Next state function
block) Error indication (Next state function block) PO
PI
Error indication (Output function block)
Predicted output characteristic i
Predicted output characteristic
Figure 2.9: Basic architecture for self-checking sequential circuit
The totally self-checking property is the usual goal when designing a circuit having OLT capability. It guarantees that there are no redundant faults (self-testing) and that the erroneous outputs generated due to any fault will not be misinterpreted as correct ones (fault secure); the fault may be either in the CUT or the checker. A number of research papers have has been published in the area of self-checking checker design using different codes [20, 34, 49, 53, 84, 86, 101, 102, 119, 128]. We now discuss some of the important coding techniques used in design of TSC circuits with pros and cons of each of them.
Parity codes: The most simple TSC circuit design is by using a single bit parity where a single check bit is added to the CUT output bits and it is calculated such that the parity of each code word is constant (odd or even). Such a parity code can detect all single or odd multiplicity errors. It is the cheapest possible error-detecting code since the check bit is only one. TSC circuit design using parity codes is reported in [84, 86]. It may be noted that if TSC circuits are designed using single bit parity codes, then all the faults that manifest themselves as even multiplicity errors cannot be detected. For such cases, circuits are synthesized specially such that all the faults in the modeled list manifest themselves as single or odd multiplicity errors. The technique presented in [34] has used single parity
bit for the entire circuit. To limit the scope of fault manifestation, each primary output is synthesized independently and so there is no sharing of logic gates among any pair of output bits. As a result, faults in any block can imply at most one output error. The single bit parity technique mandates no logic sharing among any two outputs. So it may result in high area overhead for some circuits. In order to reduce area overhead, the multiple-parity-group technique was introduced in [39, 119] that allows logic sharing among some outputs. This technique partitions the primary outputs into different parity groups. It was shown that logic sharing can be allowed among the outputs that correspond to different parity groups and that would still result in faults changing only a single output bit. The outputs of the same parity group are verified using a TSC parity checker.
m-out-of-n codes: An m-out-of-n code word has exactly m 1s out of total n bits.
m-out-of-n code is an unordered code i.e., no two code words xand y are present such that x has 1 in every bit position where y has a 1. An example of m-out-of-n code for TSC circuit design can be found in [20]. Simple inspection of the results presented is enough to illustrate the complexity of checkers based on such unordered codes compared to a parity checker. They were not widely adopted since they are much more expensive to implement than parity based schemes.
Berger codes: A Berger code consists of an information part and a check part, which is the binary representation of the number of 1s in the information part. So, it is an unordered code. TCS circuits using this methodology can be found in [21, 112]. Area overheads of the self-checking circuits designed using Berger codes are higher compared to ones designed using parity based schemes.
As a practical application, the residue code technique is used in [49] for design of self checking modulo multiplier, which is used in various cryptographic systems. In another work [128], D. P. Vasudevan and P. K. Lala have proposed a new approach for designing of self checking carry select adder of arbitrary size and the adder can detect both permanent and transient s-a faults on-line. The area overhead for making circuits totally self checkable is usually not high. A number of design and synthesis constraints are, however, required by the coding technique based methodologies to control the scope of fault propagation. For example, the method reported in [53] requires that all inverters be pushed to the primary inputs and for the scheme proposed in [34] there should be no logic sharing within a single parity group. Since these techniques require some special properties in the circuit structure, they require re-synthesis and re-design. So, OLT schemes based on design of TSC circuits using coding theory are intrusive in nature.
To address the issue of intrusiveness of coding theory based OLT schemes, weight based
codes are used [31], where a weight is assigned to each output (information) bit and the sum of weights of the output (information) bits, which have value 1, represent the check bits.
Weight-based codes can distinguish between errors changing output bits from 1 to 0 and from 0 to 1, because both these errors result in a different weight. So they do not require any special synthesis constraints to restrict the fault manifestation. Further, such codes are positional ones, i.e., the check bits are a function of the erroneous bits as well as their positions in the output (which is determined by the individual weights assigned to the output bits). Thus, they can have high fault detection capabilities. The only drawback of using weight based codes is the high area overhead compared to Berger, parity orm-out-of-ncodes.