Literature review: On-line Testing of Digital VLSI Circuits and Decision
2.3 Desired features of OLT schemes
2.3.3 OLT schemes for circuits at higher description level
It has been observed that the partial replication based OLT schemes [9,12] at gate level satisfy almost all efficient parameters of OLT, i.e., non-intrusive, architecture independent, low area and power overheads, low detection latency, etc. However, these schemes are not scalable to handle large circuits because they work at gate level and the test pattern generation time of these schemes are quite high even for moderate sized circuits. So, testing at gate level becomes a complicated and time consuming task for complex circuits. To overcome this problem, researchers are interested to test the circuits at higher level of abstraction using high level fault models. However, testing at higher level is a challenging task due to lack of well accepted fault models, unlike at the gate level, where single s-a fault model is well accepted. But it is verified that there exists good correlation between high level fault models and gate level fault models [25, 94], further gate level fault models have good correlation with physical defects. So, there exists indirect mapping between high level fault models and physical defects [133]. Since testing at lower levels (say gate level) using lower level fault models (say stuck-at-fault model) is scalable only up to certain extent (about 30K gates and 500 flip flops), so high level fault models are used to test the circuits at higher abstraction levels. In other words, even though gate level fault models are highly correlated to real defects, they are not scalable. This difficulty is addressed by developing high level fault models, testing of circuits using these fault models at higher abstraction levels and analyzing test quality by indirect mapping of faults versus physical defects [92, 97, 117].
Now we discuss some high level fault models which are based on behavioral or functional description of the circuit. These high level fault models are designed to provide good correlation with the gate level fault models. In [56], Anton Karputkin and Jaan Raik have proposed a set of behavioral fault models that target detection of stuck at faults in gate level implementations of the RTL designs. Experiments on a set of ITC’99 benchmarks show that the proposed fault models achieve high gate level stuck-at fault coverage (average of 86%). F.
Coron et al. [25] proposed an RTL fault model which assumes that all the statements in the high level description are executed at least once and their fault effects are propagated to the primary outputs. This fault model captures the single stuck at bit faults on all assignment
statements based on a set of predefined rules. They have achieved a correlation coefficient about 77% between RTL and gate level fault coverages. The fault model at RTL presented in paper [59] is based on code validation techniques used in software testing. Results show that the RTL fault coverage obtained by using this fault model based methodology has a close match with the gate-level fault coverage. The mixed hierarchical functional fault models reported in paper [94] are designed to test sequential cores inside the Systems on a Chip (SoC). The fault models proposed in this paper, based on combination of hierarchical and functional fault models provide high fault coverage for sequential circuits. It is shown by experiments that these fault models cover more than 90% of gate-level stuck-at faults for testing of sequential cores.
Since last decade, a number of high level testing schemes have been proposed using different high level fault models. Among them the number of OLT schemes is very few compared to off-line mode of testing. Now, we start with some off-line testing schemes followed by existing OLT schemes at higher level. Pradip A. Thaker et al. [117] developed an RTL fault model and fault injection algorithm based on application of stratified sampling theory and stratum weight extraction techniques where the RTL fault coverage of a module tracks the gate-level fault coverage within error bounds predicted by the random sampling technique. An RTL Automatic Test Pattern Generation (ATPG) scheme [68] was proposed by Li et al., which is based on clustering of circuit states at higher description level, termed as behavioral phases. These phases represent the circuit functionality more explicitly, thus, simplifies the representation to ease the testing. A series of works have been proposed by Raimund Ubar et al. [92, 93], for generation of hierarchical test patterns for sequential circuits using HLDDs. Experimental results show that these schemes have achieved high fault coverage (average of 89% in [92] and avegage of 91% in [93]) and low test generation time for some benchmark circuits. Reinsalu et al. in [97,98] have proposed a deductive method (based on bit coverage fault model) for RTL fault simulation using high level decision diagrams.
Experimentally they have shown that good fault coverage (average of 90% in [98] and average of 86% in paper [97]) and shorter run-times are achieved with this method in comparison to gate level fault simulation. A new off-line testing scheme for RTL circuits has proposed by Mohammad Mirzaei et al. in [74]. This scheme introduces hybrid canonical data structure based on a decision diagram for generation of test patterns from the arithmetic model of a RTL circuit. Results illustrated that the scheme achieves high fault coverage (average of 93%) with very short processing time and minimum memory usage.
All the above testing schemes at RTL are purely based on off-line mode of testing and hence cannot detect the faults that develop during normal operation. There are very few
works on OLT of VLSI circuits at RTL. The first work in this direction [58] was presented by Ramesh Karri and Balakrishnan Iyer. This Concurrent Error Detection and Diagnosis (CEDD) technique is based on replication of model operations and the replicated operations are executed with the different functional units in the idle computation clock cycles. The outputs obtained from these functional units are compared and, thus, faulty units are detected. Although the technique has low area overhead but the main disadvantage of this scheme is that, it is difficult to find the idle computation clock cycles of functional units of a system; so it has long latency. Further, now-a-days systems are designed to achieve parallelism by keeping the functional units busy in all clock cycles. Since the scheme relays on execution of replicated operations with different functional units, thus this technique cannot be applied to the operations where there is no secondary functional units to execute the replicated operations [58].
In another work, Ramesh Karri and KAijie Wu [57] developed an RTL Concurrent Error Detection (CED) technique based on algorithm level re-computing using allocation diversity and data diversity. In the case of allocation diversity technique, the operation-to- operator allocation in the normal computation and the re-computation cases are different, whereas in the data diversity technique, shift operands are applied to the re-computation.
This time-redundancy-based CED scheme achieves high fault coverage with a very low area overhead. However, this scheme has high time overhead or fault detection latency because it performs normal computation and re-computation at different times and compares their results. O. Goloubeva, M. Sonza Reorda and M. Violante [43] presented a behavioral RTL CED technique that deals with re-computation of the design operations with shifted operands. This scheme has been applied to two data dominated benchmark circuits; i.e., ELLIPF and DIFFEQ, where the fault coverage of functional units are found to be high.
From the above discussion we may state that the OLT schemes at higher abstraction level have the following issues−i) These schemes depend on idle time of different functional units of the CUT, so, they have high latency. ii) Since these schemes require some special properties in the circuit structure, they require re-synthesis and re-design of the original circuit. So, these OLT schemes are intrusive in nature. iii) These schemes are not architecture independent, since they always require secondary functional units for OLT. So, these schemes cannot be directly applied to all types of circuits.
To retain the advantages of partial replication based OLT schemes at gate level reported in [9, 12, 13], in this thesis we aim at developing a partial replication based OLT scheme at RTL. However, unlike the use of OBDD for gate level representation, in RTL we use High Level Decision Diagram (HLDD).