On-line Testing at Register Transfer Level
5.4 Generation of exhaustive set of F D-control-patterns and design of F N -detectorand design ofF N-detector
5.4.1 Design of F N -detector
TheF N-detector runs in parallel with the Circuit Under Test (CUT) by tapping the control signals and cone outputs (values of registers). The interconnection of the CUT and the F N-detector is shown in Figure 5.10. If an F D-control-pattern appears in the CUT and it results in faulty output, then the F N-detector makes the status as high to indicate that fault has occurred in the CUT. We first illustrate the design of theF N-detector for theF D- control-patternh1, d,1,0i(say f d), shown in Figure 5.11. Following that, we shall discuss a generalized procedure for its design.
CUT
FN−detector
status control signals
cone outputs
<V1+, V2+,...>
Outputs Inputs
<sel1,sel2,...>
tapping lines
Figure 5.10: Interconnection of the CUT and theF N-detector.
As already discussed, in case of f d = h1, d,1,0i the value of V1+ becomes 0 under fault F1, whereas in the normal case it has non-zero values. So, for detection of F1 the F N-detector needs to monitor control signals (hsel1, sel2, sel34, sel56i) and the cone output (V1+). Checking the occurrence of fault can be accomplished in two clock cycles. The timing diagrams of the CUT and the F N-detector are shown in Figure 5.12. The F N-detector runs in parallel with the CUT and both are driven by the same clock. In the first clock cycle, the F N-detector checks whether the values of the control signals generated by the CUT are same asf d (i.e., hsel1, sel2, sel34, sel56i=h1, d,1,0i); this can be simply verified by measuring only the control signals of the CUT and measuring the value of cone output (i.e., V1+) is not required (shown by the 1st dotted line in Figure 5.12). Following that, in the next clock cycle the F N-detector examines if the output of the cone matches the value under faulty condition, i.e.,hV1+= 0i; this can be verified by measuring only the cone output and the values of control signals are not necessary to be measured. Again, while considering one cone, the output of other cones are not required to be measured. Since we have considered the cone for V1+, thus, the value of V2+ is not required to be measured. So the cone outputs measured in second clock cycle are hV1+, V2+ = 0, dk2i (shown by the 2nd dotted line in Figure 5.12), where dk2 representsk2-bits as don’t care values. If it happens,
s0
s1
sf
s2 fault status
t3:<else>/0
t8:<else>/0 t4:<else>/0
initial state
final state
intermediate states
1+, V2+>
t5:<TRUE>/1
<sel1,sel2,sel34,sel56,V
t1:<1,d,1,0,dk
1,dk
2>/0
t2:<d,d,d,d,0,dk
2
t6:<d,1,1,1,dk
1,dk
2>/0 t7:<d,d,d,d,dk
1,0>/1
>/1
Figure 5.11: State transition diagram for the F N-detector.
then the status signal becomes high which indicates that fault (F1) has occurred in the CUT.
The state transition diagram of the F N-detector of the CUT to detect F1 is shown in Figure 5.11. In the detector, the transitions t1, t2 and t3 correspond to f d. The F N- detector starts from its initial state s0 and reaches the intermediate states1 when the CUT satisfies the values of control signals hsel1, sel2, sel34, sel56i =h1, d,1,0i. This is captured by the transition t1 : h1, d,1,0, dk1, dk2,i/0. It may be noted that enabling condition of t1 is h1, d,1,0, dk1, dk2,i, which implies that the values of sel1 = 1, sel2 = d, sel34 = 1, sel56 = 0, V1+ =dk1 and V2+ =dk2, wheredk1 and dk2 representk1-bits and k2-bits as don’t care values, respectively. The output bit of t1 is 0, which indicates fault has not yet been detected. In simple words, for eachF D-control-pattern there is a transition from initial state to intermediate state with enabling signals same as the F D-control-pattern. From state s1, the detector needs to verify whether F1 has occurred in the CUT in the next clock cycle.
This is accomplished by transition t2 : hd, d, d, d,0, dk2i from s1. The enabling condition of t2 implies the values of control signals and V2+ are don’t cares and the value of V1+ is 0 (faulty output). Thus, the transition t2 leads the F N-detector to the final state sf yielding output 1, which indicates that F1 has occurred in the CUT. If the enabling condition of
<control signals
Clock
Clock
0 1
(sel1, sel2, sel34, sel56)>
V1+, V2+)>
<control signals, cone outputs>
<Status signal>
1+, V2+) (sel1, sel2, sel34, sel56, V
<1,d,1,0>
<0,dk
2>
<cone outputs
<1,d,1,0,dk
1,dk
2> <d,d,d,d,0,dk
2>
FN−detrctorCUT
1st 2nd 3rd 4th
Figure 5.12: Timing diagram of the CUT versusF N-detector under faultFi.
t2 is not satisfied in the state s1 (i.e., V1+ 6= 0), then the F N-detector moves back to the initial state s0 by the transition t3. Once the final state sf is reached, the F N-detector remains in that state forever maintaining output as 1, since the faults are assumed to be permanent. This is accomplished by transitiont5, whose enabling condition is always TRUE.
In similar way, the working of F D-control-pattern hd,1,1,1i with faulty output (V2+= 0) can be explained using transitionst6, t7 and t8. Thus, the F N-detector has three type of states; a) an initial state (s0), b) a final state (sf) and c) a set of intermediate states, for eachF D-control-pattern. Thus, the F N-detector is an FSM given by six-tuples
GF N−detector =hS, s0,Σ, δ, Y, sfi, (5.3) where S is the set of states, s0 is the initial state, Σ is the input variables (control signals and cone outputs),δ :S×Σ→S is the transition function,Y :S×Σ→ {0,1}is the output function and sf is the final state. The F N-detector can be constructed by using the steps given below for each F D-control-pattern. Let f d be an F D-control-pattern that manifests
faultFi through cone output Vm+ with faulty response Rf. 1. Create an initial state s0 and a final state sf.
2. For eachF D-control-pattern f d, repeat Step 3 and Step 4.
3. Create an intermediate state sk and add a transition tk from state s0 to sk. Inputs of tk are the same as the values of the signals in f d co-joined with the cone outputs, which are don’t cares. Output of tk is 0.
4. Add a transitiontlfromsk tosf. Input oftlincludes don’t cares for the control signals co-joined with the cone outputs, which are also don’t cares except for the cone Vm+. The value ofVm+ is equal toRf. The output of tl is 1.
5. From each intermediate state sk, add a transition tos0. The enabling condition of the transition is any value of the control signals and the cone outputs other than the one corresponding to the enabling condition of the transition fromsk tosf. The output of the transition is 0.
6. Add a self loop ats0, whose enabling condition is any value of control signals and cone outputs other than the ones corresponding to the enabling conditions of the transitions emanating from s0. The output of the transition is 0.
7. Add a self loop at sf, whose enabling condition is TRUE, i.e., any value of control signals and cone outputs, and its output is 1.