Intel Corporation
Intel Corporation
Silicon Technology Review
Silicon Technology Review
Ken David
Ken David
Director, Components Research
Director, Components Research
SEMI
SEMI
–
–
Strategic Business Conference
Strategic Business Conference
April 2003
Agenda
Agenda
y
y
Corporate Mission
Corporate Mission
–
– Leadership in TechnologyLeadership in Technology –
– Leadership in IntegrationLeadership in Integration
y
y
How do we continue to succeed?
How do we continue to succeed?
–
– InvestmentsInvestments –
– Research and DevelopmentResearch and Development –
– Manufacturing ExcellenceManufacturing Excellence
y
y
Supplier Expectations
Supplier Expectations
y
Entering A New Era
Entering A New Era
Memory
Memory
Microprocessors
Microprocessors
Converged
Converged
Computing and
Computing and
Communications
Leadership by Technology
Leadership by Technology
Leadership by Integration
Leadership by Integration
Intel
Intel®® PXA800F ProcessorPXA800F Processor IntelIntel®® Mobile TechnologyMobile Technology
Intel
Intel®® OnChip OnChip Flash Flash 4MB/512kB 4MB/512kB Intel
Intel®®
MicroSignal
MicroSignal
Architecture
Architecture
Intel
Intel®® XScale
XScale™™ Core
Core
& Peripherals
& Peripherals
How do we continue to lead?
How do we continue to lead?
y
y
Commitment through investments
Commitment through investments
y
y
Commitment through advanced research and
Commitment through advanced research and
development
development
–
–
new technologies
new technologies
y
y
Continued, successful implementation of
Continued, successful implementation of
Moore’s Law
Moore’s Law
y
Intel Capital Expenses
Intel Capital Expenses
0
0
5
5
10
10
15
15
20
20
25
25
Intel
Intel Competitor 1Competitor 1 Competitor 2Competitor 2 Competitor 3Competitor 3
Billions($)
Billions($)
Capital Ex: Intel v. Competitors (00
Capital Ex: Intel v. Competitors (00 -- 03)03)
*Estimate
Intel R&D Investment ($M)
Intel R&D Investment ($M)
$4,000
$517 $618
$780 $970
$1,111$1,296
$1,808
$2,347$2,509
$3,111
$3,897 $3,800
$4,000 est.
1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003
Worldwide Intel R&D Presence
Worldwide Intel R&D Presence
75+ labs and over 7,000 R&D
75+ labs and over 7,000 R&D
professionals
professionals
Decentralized Approach Fosters Innovation Decentralized Approach Fosters Innovation Illinois Illinois USA USA Washington Washington USA USA Oregon Oregon USA USA California California USA USA Tsukuba Tsukuba Tokyo Tokyo Japan Japan Delhi Delhi Bangalore Bangalore Mumbai Mumbai India India Arizona Arizona USA USA Beijing Shanghai China Haifa, Israel Haifa, Israel Nizhny Nizhny Novgorod, Novgorod, Sarov Sarov Russia Russia Braunschweig
Braunschweig,, Ulm Ulm Germany Germany Gdansk, Poland Gdansk, Poland Barcelona, Barcelona, Spain Spain Glasgow, Glasgow, Scotland Scotland Copenhagen, Copenhagen, Denmark Denmark Shannon, Ireland Shannon, Ireland Stockholm, Stockholm, Sweden Sweden Nice, France Nice, France
New Mexico, USA
New Mexico, USA
Swindon
Swindon, UK, UK
Illinois Illinois USA USA Washington Washington USA USA Oregon Oregon USA USA California California USA USA Tsukuba Tsukuba Tokyo Tokyo Japan Japan Delhi Delhi Bangalore Bangalore Mumbai Mumbai India India Arizona Arizona USA USA Arizona Arizona USA USA Beijing Shanghai China Haifa, Israel Haifa, Israel Nizhny Nizhny Novgorod, Novgorod, Sarov Sarov Russia Russia Braunschweig
Braunschweig,, Ulm Ulm Germany Germany Gdansk, Poland Gdansk, Poland Barcelona, Barcelona, Spain Spain Glasgow, Glasgow, Scotland Scotland Copenhagen, Copenhagen, Denmark Denmark Shannon, Ireland Shannon, Ireland Stockholm, Stockholm, Sweden Sweden Nice, France Nice, France
New Mexico, USA
New Mexico, USA
Swindon
• Research Groups are de-centralized
• Multiple sites
• Central Technology Development groups
• Logic: Hillsboro, Oregon
• Memory: Santa Clara, California
• Packaging: Chandler, Arizona
• Copy Exactly! from Development into
Manufacturing
• Fastest and Highest Volume Manufacturing
Ramp
Technology Focus:
Technology Focus:
Technology Focus: Logic
Technology Focus: Logic
Actual Forecast
Process Name P858 Px60 P1262 P1264 P1266 P1268 P1270
1st Production 1999 2001 2003 2005 2007 2009 2011
Lithography Node 180 130 90 65 45 32 22nm
Gate Length 130 70 50 30 20 15 10nm
Fab Development Research
Leadership through
Leadership through
Technology
Technology
y
y
Mission
Mission
–
–
to continue to provide leading edge
to continue to provide leading edge
technology in computing and communications
technology in computing and communications
y
y
Financial Challenges
Financial Challenges
y
y
Technology Challenges
Technology Challenges
–
– Increasing chip complexityIncreasing chip complexity –
– aggressive scalingaggressive scaling
–
– new materialsnew materials
–
– added features (integrated capabilities)added features (integrated capabilities)
–
Moore’s Law.... in the
Moore’s Law.... in the
beginning
beginning
1965 Transistor Projection
Moore’s Law Today
Moore’s Law Today
Moore’s Law Today
1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 1,000,000,000
1970 1980 1990 2000 2010
8008
8086 286
8080
386™ Processor 486™ DX ProcessorPentium® Processor
Pentium® II ProcessorPentium® III Processor Pentium® 4 Processor
Itanium ® Processor 410 Million
Moore’s Law Economics
Moore’s Law Economics
(Source: Intel, VLSIR)
(Source: Intel, VLSIR)
0.04 0.04 0.05 0.05 0.04 0.04 $B/kwpm $B/kwpm 30
30 -- 3535
~77 (200mm
~77 (200mm- -equivalent) equivalent) 40 40 20 20 Fab Fab capacity, capacity, kwpm kwpm 3 3 2 2 0.9 0.9
Fab cost, $B
Fab cost, $B
Evolution of Intel Process
Evolution of Intel Process
1997 1999 2001 2003 2005 2007 2009 2011
Node 0.25µm 0.18 µm 130nm 90nm 65nm 45nm 32nm 22nm
Litho DUV Æ 193nm Æ Æ 193/157 ? ?
Metal Al Æ Cu Æ Æ Æ Æ ?
ILD SiO2 SiOF Æ SiOC Æ Æ ? ?
Gate Ox SiO2 Æ Æ Æ High-k? ? ? ?
Gate
Electrode Poly Æ Æ Æ Æ Metal? ? ?
New Structures
New Processes
Extending Moore’s
Law! New
Success in 90nm development
Success in 90nm development
Silicide Layer
Silicon Gate Electrode
1.2 nm SiO2 Gate
Oxide
Strained Silicon
50nm
Low K ILD
Cu
interconnects Advanced Cu barriers
90nm Node 2003
Driving Moore’s Law Further
Driving Moore’s Law Further
30nm Prototype (IEDM2000)
20nm Prototype (VLSI2001)
25 nm
15nm
15nm Prototype
15nm Prototype
(IEDM2001)
(IEDM2001) 50nm Length
(IEDM2002)
65nm Node 2005
45nm Node 2007
10nm Prototype
10nm Prototype
(ITJ 2002)
(ITJ 2002)
32nm Node 2009
Working on Advanced Transistor Architecture
Working on Advanced Transistor Architecture
Î
Î
New Process
New Process
Î
Î
Need New Materials
Need New Materials
Gate
Gate
Drain
Drain
Source
Source
World record breaking NMOS
Intel Lithography Roadmap
Intel Lithography Roadmap
10 100 1000
i-line DUV i-line
DUV DUV 193nm DUV
193nm 193nm 157nm 193nm
EUV 157nm
EUV EUV
1993 1995 1997 1999 2001 2003 2005 2007 2009 2011 2013
1/2 Pi
tc
h (
n
m)
130nm Node
90nm Node
65nm Node
45nm Node
32nm Node
“Dual Wavelength Strategy”
157nm Lithography
157nm Lithography
2001 1999 2000
157nm lithography is maturing:
z Research tools shipping in 2003
z Development tools scheduled for 2004
EUV Lithography - Full Field ETS images
(using 0.1 NA system)
4x5 matrix
152 mm2, 4X
Reflective Mask 100 nm contacts 1:1
100 nm contacts 1:1
100 nm Elbows 1:1 100 nm Elbows 1:1
200 mm Wafer 200 mm Wafer
80 nm Elbows 1:1 80 nm Elbows 1:1
24 x 32.5 mm2 field
Printing 80 nm images at 0.1 NA is equivalent
Leadership By Integration
Leadership By Integration
2004
2004 20062006 2002
2002
Package Level Integration
Package Level Integration
Stacked discrete chips and packages
Stacked discrete chips and packages
Silicon Level Integration
Silicon Level Integration
Functions combined on single chip
Functions combined on single chip
Functions on Discrete Chips
Functions on Discrete Chips
Flash, Applications processors, Cellular chipsets
Flash, Applications processors, Cellular chipsets
Computing + Communications on One Chip
Wireless Internet on a Chip
Wireless Internet on a Chip
by Flash+Logic Integration
by Flash+Logic Integration
Intel
Intel®® PXA800F ProcessorPXA800F Processor
90nm Transistor Gate
90nm Transistor Gate
90nm
Logic
Logic
0.16µm
0.16µm22 Flash CellFlash Cell
Flash
Flash IntelIntel®® OnChip OnChip Flash Flash 4MB/512kB 4MB/512kB Intel
Intel®®
MicroSignal
MicroSignal
Architecture
Architecture
Intel
Intel®® XScale
XScale™™ Core
Core
& Peripherals
& Peripherals
Continued Manufacturing
Continued Manufacturing
Excellence
Excellence
y
y
0.13
0.13
µ
µ
m manufacturing leadership
m manufacturing leadership
y
y
Worldwide Presence
Worldwide Presence
y
y
Intel Manufacturing Philosophy
Intel Manufacturing Philosophy
–
– Technology Development and Manufacturing LinkedTechnology Development and Manufacturing Linked –
– Copy Exact! Transfer of ProcessesCopy Exact! Transfer of Processes –
– Manufacturing Efficiency Manufacturing Efficiency ÆÆ 300mm Production300mm Production –
Intel’s High Volume Manufacturing Sites
Intel’s High Volume Manufacturing Sites
Ireland Ireland Fab 14/24 Fab 14/24 Israel Israel Fab 8/18 Fab 8/18 Oregon Oregon Dev D1C/D1D Dev D1C/D1D Fab 15/20 Fab 15/20 California California Dev D2 Dev D2 Colorado Colorado Fab 23 Fab 23 Arizona Arizona Fab12/22 Fab12/22 New Mexico New Mexico Fab 11/11X Fab 11/11X Mass. Mass. Fab 17 Fab 17 Costa Rica Costa Rica
San Jose A/T San Jose A/T
A/T Dev
A/T Dev MalaysiaMalaysia
Penang A/T Penang A/T Kulim A/T Kulim A/T China China Pudong A/T Pudong A/T Philippines Philippines Manila A/T Manila A/T Cavite A/T Cavite A/T Washington Washington Systems Mfg. Systems Mfg. Board Mfg. Board Mfg.
Kulim Board/Module Mfg.
Kulim Board/Module Mfg.
Brazil
Brazil
Sub
Sub--con Mfg.con Mfg.
Thailand
Thailand
Sub
Sub--con Mfg.con Mfg.
Sub
Sub--con Mfg.con Mfg.
Taiwan
Taiwan
Sub
Sub--con Mfgcon Mfg Sub
Sub--con Mfg.con Mfg.
Sub
Sub--con Mfg.con Mfg.
.
0.13µm(130nm) Leadership
0.13µm(130nm) Leadership
F20
F20 D2D2 F22F22
F17 F17
2001
2001 20022002 20032003
200mm
Q1
Q1 Q2Q2 Q3Q3 Q4Q4 Q1Q1 Q2Q2 Q3Q3 Q4Q4 Q1Q1 Q2Q2 Q3Q3 Q4Q4
Nearest CPU
Nearest CPU
Competitor
Competitor
D1C
D1C
F11X
F11X
300mm
300mm
Breaking Away from the competition
Breaking Away from the competition
Wafer Starts
Logic Development:
Linking 300mm Research, Development, and
Production
D1C: 300mm 130nm Production 90nm Development
RP1: 300mm Research RP1: 300mm
RP1: 300mm
Research
Research
D1C/F25: 300mm
D1C/F25: 300mm
0.13µm Production
0.13µm Production
90nm Development
90nm Development
and Production
and Production
F20: 200mm
F20: 200mm
0.13µm Production
0.13µm Production
D1D: 300mm
D1D: 300mm
65nm Development
65nm Development
Manufacturing Efficiency
Manufacturing Efficiency
200 mm
200 mm 300 mm300 mm
$ Capital spending per die of Capital spending per die of output capacityoutput capacity
.18um
Scale: Leading Edge Capacity
Scale: Leading Edge Capacity
Q
Q Q+1Q+1 Q+2Q+2 Q+3Q+3 Q+4Q+4 Q+5Q+5 Q+6Q+6 Q+7Q+7 WSPWWSPW
**Source: Intel Estimates **Source: Intel Estimates
(Quarter in Ramp)
(Quarter in Ramp)
0.13u
0.13u
90nm
90nm
D2
D2
F20
F20
F11X
F11X
300mm
300mm
F17
F17
D1C
D1C
300mm
300mm
D1C
D1C
F24 F24
F11X
F11X
F22
Supplier Expectations
Supplier Expectations
y
y
Manufacturing excellence
Manufacturing excellence
–
– Timely, costTimely, cost--efficient support during HVM rampefficient support during HVM ramp –
– Quality systems Quality systems
y
y
Advanced Development
Advanced Development
–
– New equipment and capabilities matched with Intel’s New equipment and capabilities matched with Intel’s roadmap
roadmap
–
– Process DevelopmentProcess Development
y
y
Research
Research
–
Summary
Summary
Intel is committed to the future technologies
Success starts with the present
•
90nm technology innovation
•
90nm ramp in 2H’03
...and leads to the future
•
continued extension of Moore’s Law
•
Package level integration
For further information on Intel's silicon technology and Moore’s Law, please visit the Silicon Showcase
